Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler

ABSTRACT

A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention improves electrical properties of dual damascene interconnections and minimizes defects.

[0001] This application is a continuation-in-part (CIP) of applicationSer. No. 10/081,661 filed on Feb. 22, 2002, Ser. No. 10/114,274 filed onApr. 2, 2002 and Ser. No. 10/437,529, filed on May 14, 2003, assigned tothe assignee of the present application, the contents of which areincorporated herein by reference in their entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a microelectronic device, andmore particularly, to a method of fabricating dual damasceneinterconnections of a microelectronic device.

[0004] 2. Description of the Related Art

[0005] As microelectronic devices become more efficient and highlyintegrated, multi-layered interconnections are more widely used. Toobtain a reliable device including multi-layered interconnections, eachinterconnection layer are formed in a planar fashion. Thus, dualdamascene interconnections have become strongly relied upon.

[0006] Meanwhile, in today's highly integrated microelectronic devices,a design rule has been reduced to 0.18 μm or less, and even to 90 nm.Such a small design rule brings about increases in RC delay, cross talk,and power consumption. To solve these problems, an interlayer dielectric(ILD) should be formed of a low-k dielectric material layer. As aresult, the need to further develop techniques of fabricating dualdamascene interconnections using a low-k ILD has greatly increased.

[0007] Methods of fabricating dual damascene interconnections aredisclosed in U.S. Pat. No. 6,057,239, and in J. Vac. Sci. Technol. A19(2001) p. 1388, by P. Jiang et al. However, the method disclosed in U.S.Pat. No. 6,057,239 uses an ILD formed of only an oxide layer, adielectric constant of which is about 4 to 4.3.

[0008] Also, when a trench is etched and cleaned, an etch stop layer maybe etched to expose interconnections, thus degrading electricalproperties of the interconnections. In the thesis by P. Jiang et al.,before a trench is etched, a via is filled with an organic filler, suchas a bottom anti-reflection layer (ARL), to prevent degradation ofelectrical properties. However, because both the organic filler and aphotoresist pattern are organic materials having similar etch rates, thephotoresist pattern is almost removed during etching of the organicfiller formed on an ILD. Thus, when the ILD is etched to form a finaltrench, the photoresist pattern cannot be used as an etch mask. Toprevent this problem, as shown in FIG. 1A, before a photoresist pattern22 is formed, an organic filler 20 is etched using an etchback processuntil the organic filler 20 remains only in a via 19. However, thisprocess is very complicated. In addition, as illustrated with dottedcircles 24 in FIG. 1B, a low-k ILD 18 is not etched and remains on theorganic filler 20 because of a difference in etch rate between theorganic filler 20 and the low-k ILD 18. The remaining low-k ILD 18generates fences 26 as shown in FIG. 1C. In FIGS. 1A and 1B, referencenumeral 10 denotes a substrate, 12 denotes a lower ILD, 14 denotes lowerinterconnections, and 16 denotes an etch stop layer.

[0009] To prevent the fence defects, if the organic filler 20 is etchedback by over-etching such that a portion of the via 19 is filled withthe organic filler 20, a thickness deviation of a photoresist layerbecomes very great between a high via-density region and a lowvia-density region. As a result, a depth of focus (DOF) margin decreasesin a photolithographic process.

[0010] Further, during an exposure process for forming the photoresistpattern 22, basic materials, such as amine, may be diffused from the ILD18 through the organic filler 20 to the photoresist layer, therebyresulting in photoresist poisoning.

[0011] Therefore, a method of fabricating reliable dual damasceneinterconnections without degrading electrical properties of a low-k ILDis required.

SUMMARY OF THE INVENTION

[0012] The present invention provides a method of fabricating reliabledual damascene interconnections in a low-k interlayer dielectric (ILD).

[0013] The present invention also provides a method of fabricatingnon-defective dual damascene interconnections.

[0014] In accordance with an aspect of the present invention, there isprovided a method of fabricating dual damascene interconnections, whichcomprises (a) forming a hybrid dielectric layer having a dielectricconstant of 3.3 or less on a substrate; (b) forming a via in thedielectric layer; (c) filling the via with a carbon-free inorganicfiller; (d) partially etching the inorganic filler filling the via andthe dielectric layer to form a trench, which is connected to the via andin which interconnections will be formed; (e) removing the inorganicfiller remaining in the via; and (f) completing interconnections byfilling the trench and the via with an interconnection material.

[0015] In accordance with another aspect of the present invention, thereis provided a method of fabricating dual damascene interconnections,which comprises (a) forming an organo silicate glass layer on asubstrate; (b) forming a via in the organo silicate glass layer; (c)filling the via with an HSQ-based filler; (d) partially etching theHSQ-based filler filling the via and the organo silicate glass layer toform a trench, which is connected to the via and in whichinterconnections will be formed; (e) removing the HSQ-based fillerremaining in the via; and (f) completing interconnections by filling thetrench and the via with an interconnection material.

[0016] Preferably, the organo silicate glass layer is formed usingchemical vapor deposition (CVD).

[0017] In accordance with yet another aspect of the present invention,there is provided a method of fabricating dual damasceneinterconnections, which comprises (a) forming a lower interconnection ona substrate; (b) forming an etch stop layer on the lowerinterconnection; (c) forming an organo silicate glass layer usingchemical vapor deposition (CVD) on the etch stop layer; (d) forming avia through the organo silicate glass layer to expose the etch stoplayer; (e) filling the via with an HSQ-based filler; (f) processing thesurface of the HSQ-based filler using plasma; (g) forming ananti-reflection layer (ARL) on the plasma-processed surface of theHSQ-based filler; (h) partially etching the ARL, the HSQ-based fillerfilling the via, and the organo silicate glass layer to form a trench,which is connected to the via and in which interconnections will beformed; (i) removing the HSQ-based filler remaining in the via; and (k)completing interconnections by filling the trench and the vias with aninterconnection material.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The foregoing and other objects, features and advantages of theinvention will be apparent from the more particular description of apreferred embodiment of the invention, as illustrated in theaccompanying drawings in which like reference characters refer to thesame parts throughout the different views. The drawings are notnecessarily to scale, emphasis instead being placed upon illustratingthe principles of the invention.

[0019]FIGS. 1A through 1C are cross-sectional views and a scanningelectron microscope (SEM) image illustrating a conventional method offabricating conventional dual damascene interconnections.

[0020]FIGS. 2 through 13 are cross-sectional views illustrating a methodof fabricating dual damascene interconnections according to anembodiment of the present invention.

[0021]FIGS. 14A, 14B, 15A, 16A, 17A, 17B, 18 and 19 are SEM imagesshowing a test sample fabricated according to the present invention.

[0022]FIGS. 15B and 16B are SEM images showing a contrastive sampleaccording to a conventional method.

[0023]FIGS. 20 through 24 are graphs showing electrical properties of adevice fabricated according the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0024] In the present invention, an interlayer dielectric (ILD) may beformed of a hybrid low-k dielectric material. The hybrid low-kdielectric material has advantages of both organic and inorganicmaterials. The hybrid low-k dielectric material shows low-kcharacteristics like an organic material. Also, the hybrid low-kdielectric material can be formed using a conventional apparatus andprocess since it has a modified structure from a conventional inorganicsilicate oxide. And, the hybrid low-k dielectric material is thermallystable like an inorganic material. In particular, when the ILD is formedof a hybrid low-k dielectric material, whose dielectric constant is 3.3or lower, RC delay is prevented and cross talk and power consumption canbe minimized.

[0025] In the embodiments of the present invention, a via filler may beformed of a material which has a good gap filling characteristic andwhich has an etch rate substantially equal to that of a low-k ILD, orhas a high etch selectivity with respect to the low-k ILD, depending onetching methods or conditions. In particular, the via filler may beformed of a carbon-free inorganic material so that it can be dry etchedat the same etch rate as the ILD and wet etched at a much higher ratethan the ILD. Also, the via filler may be formed of a material that canfunction as a barrier layer to basic materials, such as nitrogen andamine. In specific embodiments of the present invention, a via fillermay be formed of a material comprising a light absorption material or adissolution inhibitor for a photoresist developing solution. Thus, anetch stop layer for protecting a lower interconnection is not damaged,photoresist poisoning is prevented, a DOF margin is improved in aphotolithographic process, and fence defects, which adversely affectelectrical properties of dual damascene interconnections, are prevented.Further, robust and reliable dual damascene interconnections can befabricated, without increasing the critical dimension of a trench.

[0026] The present invention can be applied to microelectronic devices,such as highly integrated circuit semiconductor devices, processors,micro electromechanical (MEM) devices, optoelectronic devices, anddisplay devices. In particular, the present invention is highly usefulfor devices requiring high-speed characteristics, such as centralprocessing units (CPUs), digital signal processors (DSPs), combinationsof a CPU and a DSP, application specific integrated circuits (ASICs),logic devices, and SRAMs.

[0027] Herein, an opening exposing a lower interconnection is referredto as a via, and a region where interconnections will be formed isreferred to as a trench. Hereinafter, the present invention will bedescribed by way of an example of a via-first dual damascene process, inwhich, even if misalignment occurs, the size of a via can be heldconstant.

[0028] Hereinafter, a method of fabricating dual damasceneinterconnections according to an embodiment of the present inventionwill be described with reference to FIGS. 2 through 13.

[0029] As shown in FIG. 2, a substrate 100 is prepared. A lower ILD 105including a lower interconnection 110 is formed on the substrate 100.The substrate 100 may be, for example, a silicon substrate, a silicon oninsulator (SOI) substrate, a gallium arsenic substrate, a silicongermanium substrate, a ceramic substrate, a quartz substrate, or a glasssubstrate for display. Various active devices and passive devices may beformed on the substrate 100. The lower interconnection 110 may be formedof various interconnection materials, such as copper, copper alloy,aluminium, and aluminium alloy. The lower interconnection 110 ispreferably formed of copper because of its low resistance. Also, thesurface of the lower interconnection 110 is preferably planarized.

[0030] Referring to FIG. 3, an etch stop layer 120, a low-k ILD 130, anda capping layer 140 are sequentially stacked on the surface of thesubstrate 100 where the lower interconnection 110 is formed, and aphotoresist pattern 145 is formed on the capping layer 140 to define avia.

[0031] The etch stop layer 120 is formed to prevent electricalproperties of the lower interconnection 110 from being damaged during asubsequent dry etch process for forming a via and a subsequent wet etchprocess for removing the remaining filler. Accordingly, the etch stoplayer 120 is formed of a material having a high etch selectivity withrespect to the ILD 130 formed thereon. Preferably, the etch stop layer120 is formed of SiC, SiN, or SiCN, having a dielectric constant of 4 to5. The etch stop layer 120 is as thin as possible in consideration ofthe dielectric constant of the entire ILD, but thick enough to properlyfunction as an etch stop layer.

[0032] The ILD 130 is formed of a hybrid low-k dielectric material,which has advantages of organic and inorganic materials. That is, theILD 130 formed of the hybrid low-k dielectric material has low-kcharacteristics, can be formed using a conventional apparatus andprocess, and is thermally stable. The ILD 130 is formed of a hybridmaterial having a dielectric constant of 3.3 or less, to prevent an RCdelay between the lower interconnection 110 and dual damasceneinterconnections and minimize cross talk and power consumption. Mostpreferably, the ILD 130 is formed of low-k organo silicate glass (OSG).The ILD 130 formed of low-k OSG can be formed using chemical vapordeposition (CVD), more specifically, plasma-enhanced CVD (PECVD). As thecarbon content in an OSG layer increases, the dielectric constant of theOSG layer decreases but thermal and mechanical characteristics aredegraded. However, if an OSG layer is formed using CVD, the carboncontent in the OSG layer can be adjusted to appropriately control thedielectric constant and thermal and mechanical characteristics of theOSG layer. Therefore, an OSG layer formed using CVD is suitable for theILD 130. It is obvious that various changes may be made by known methodsin the source gas (e.g., carbon source gas, silicon source gas, andoxygen source gas), a CVD chamber, and fabricating conditions (e.g.,temperature and time conditions) used for forming the OSG layer usingCVD. A method of forming OSG using CVD may be a known method or methodsdisclosed in U.S. Pat. No. 6,455,445, No. 6,432,846, No. 6,514,880, No.6,559,520, No. 6,352,945, No. 6,383,955, and No. 6,410,463, and KoreanPatent No. 0364053, which are incorporated herein by reference in theirentirety as fully disclosed in the present invention. The ILD 130 isformed to a thickness of 3000 Å to 20000 Å, preferably, 6000 Å to 7000Å. However, the ILD 130 can be formed to various thicknesses by thoseskilled in the art.

[0033] Meanwhile, when dual damascene interconnections are planarizedusing chemical mechanical polishing (CMP), the capping layer 140prevents the ILD 130 from being damaged by the CMP. Thus, the cappinglayer 140 is formed of SiO₂, SiOF, SiON, SiC, SiN, or SiCN. Preferably,the capping layer 140 functions as an anti-reflection layer (ARL) in asubsequent photolithographic process for forming a trench. Accordingly,the capping layer 140 is more preferably formed of SiO₂, SiON, SiC, orSiCN. However, if damage to the ILD 130 can be prevented by controllingthe CMP process and an anti-reflective material layer is formed in asubsequent process, the formation of the capping layer 140 may beoptionally omitted.

[0034] The photoresist pattern 145 is formed by forming a layer of aphotoresist that is suitable for a light source of 248 nm or less andthen performing exposure and developing processes using a photo maskdefining a via.

[0035] Referring to FIG. 4, the ILD 130 is dry etched (147) using thephotoresist pattern 145 as an etch mask to form a via 150. The ILD 130is etched using a reactive ion beam etch (RIE) process, which uses amixture of a main etch gas (e.g., CxFy and CxHyFz), an inert gas (e.g.Ar gas), and optionally at least one of O₂, N₂, and COx. Here, the RIEconditions are adjusted such that only the ILD 130 is selectively etchedand the etch stop layer 120 is not etched.

[0036] Referring to FIG. 5, the photoresist pattern 145 is removed andthe via 150 is filled with a via filler 160. The photoresist pattern 145is processed using an H₂-based plasma and removed using a stripper.H₂-based plasma refers to plasma obtained from H₂, N₂/H₂, NH₃/H₂,NH₃/H₂, He/H₂, or a mixture thereof. If the photoresist pattern 145 isremoved using O₂-ashing, which is widely used for removing a photoresistpattern, the ILD 130 containing carbon to have organic properties may bedamaged by the O₂-based plasma. Thus, the photoresist pattern 145 ispreferably removed using an H₂-based plasma.

[0037] The via filler 160 is formed of a material that has a good gapfilling characteristic. Also, a dry etch ratio of the via filler 160 tothe ILD 130 is either about 1:1 or 4:1 or less. Further, the via filler160 is formed of a material that is etched at a higher etch rate thanthe ILD 130 in a subsequent wet etch process. Preferably, the via filler160 is formed of a material having such a characteristic that a wet etchratio of the via filler 160 to the ILD 130 is 20:1 or higher. Also,during an exposure process for forming a photoresist pattern to define asubsequent trench, basic materials, such as nitrogen and amine, includedin the ILD 130, may diffuse into a photoresist layer. Thus, the viafiller 160 is formed of a material that can prevent the diffusion of thebasic material into the photoresist layer. That is, the via filler 160is preferably formed of a carbon-free inorganic material to have a dryetch rate being substantially equal to that of the ILD 130, which is ahybrid of an organic material and an inorganic material, and a wet etchrate being much higher than that of the ILD 130. Given the foregoingconditions, HydrogenSilsesQuioxane (HSQ) is the most suitable for thevia filler 160 among carbon-free inorganic materials.

[0038] Further, the via filler 160 preferably includes a lightabsorption material or a dissolution inhibitor. The dissolutioninhibitor, which inhibits dissolution of a photoresist developingsolution, may be a material known by those skilled in the art. Thefunctions of the light absorption material and the dissolution inhibitorwill be described later. In the present invention, HSQ-based materialsrefer to not only pure HSQ but also HSQ including additives, such as alight absorption material and/or a dissolution inhibitor.

[0039] The via filler 160 is formed using spin coating to completelyfill the via 150. While it is possible to fill only the via 150 with thevia filler 160, the via filler 160 is preferably formed on the cappinglayer 140 to a predetermined thickness in consideration of processmargin control. Also, it is preferable in terms of a DOF margin that adifference between the height T1 of the via filler 160 formed in a lowvia-density region and the height T2 of the via filler 160 formed in ahigh via-density region is 2000 Å or less. The thickness of HSQ-basedmaterials can be easily controlled in consideration of variables such ascoating recipe, the space between vias 150, the critical dimension, andthe height of the via 150, and the condition (T1-T2≦2000 Å) can beeasily satisfied.

[0040] Referring to FIG. 6, the surface of the via filler 160 isprocessed using plasma 170. The plasma 170 is derived from O₂, H₂, He,NH₃, N₂, Ar, or any mixture thereof, and the plasma processing isconducted at a temperature of room temperature to 500° C. for 1 to 120seconds. The surface of the via filler 160 is densified by the plasmaprocessing. Also, the plasma processing is carried out to prevent aphotoresist developing solution from dissolving the via filler 160.Accordingly, if the via filler 160 includes a dissolution inhibitor, theplasma processing may be optionally omitted.

[0041] Referring to FIG. 7, an anti-reflection layer (ARL) 180 is formedon the via filler 160, which is processed using plasma 170. Although itis possible to form the ARL 180 using an inorganic material, the ARL 180is preferably formed of an organic material in order to be easilyremoved later. The ARL 180 is formed of an anti-reflective material thatcan absorb light of a wavelength 248 nm, 193 nm, or less, which is knownto those skilled in the art, or a material that is disclosed in U.S.patent application Ser. No. 10/400,029, commonly owned by the sameassignee and is incorporated herein by reference in its entirety asfully disclosed in the present invention. The ARL 180 is formed to athickness of 500 Å to 700 Å.

[0042] Referring to FIG. 8, a photoresist layer 185 is formed and thenexposed to light using a mask 200 defining a trench. When the lightemitted from an exposure source with a wavelength of 248 nm, 193 nm, orless is transmitted through a transmission region 201 of the mask 200and radiated onto the photoresist layer 185, acids H+ are generated froma photo acid generator included in an exposure portion 185 b of thephotoresist layer 185. Here, the ARL 180, disposed under the exposureportion 185 b, prevents rays penetrating the photoresist layer 185 frombeing reflected back to the photoresist layer 185. Accordingly, if thevia filler 160 includes a light absorption material to prevent thereflection of rays, the formation of the ARL 180 may be optionallyomitted. The acids H+ generated in the exposure portion 185 b hydrolyzethe photoresist layer 185 into a material soluble in a developingsolution. After the exposure process, acidolysis becomes more active bya post-exposure baking (PEB) process. During the exposure process andthe PEB process, the via filler 160 functions as a diffusion barrierlayer to nitrogen or amine. Accordingly, basic materials, such asnitrogen and amine, which remain in the ILD 130 due to etch gas used foretching the via 150 as well as the plasma processing for removing thephotoresist pattern (145 of FIG. 4) defining the via 150, cannot diffuseas depicted in a dotted line through the via filler 160 and neutralizethe acids H+ generated in the exposure portion 185 b, since the viafiller 160 functions as the diffusion barrier layer, thereby resultingin no photoresist poisoning.

[0043] Referring to FIG. 9, a photoresist pattern 185 a is formed. Whenthe post-exposure baked photoresist layer 185 is soaked in a tetramethylammonium hydroxide developing solution, only the exposure portion 185 bis dissolved in the developing solution. Thus, as shown in FIG. 9, thephotoresist pattern 185 a is obtained. Here, the via filler 160 is notexposed to the developing solution due to the ARL 180 disposed under theexposure portion 185 b. If the via filler 160 is processed using plasmaor includes a dissolution inhibitor, it is not damaged by the developingsolution even without the ARL 180.

[0044]FIG. 10 shows the formation of a trench 190. The ARL 180, the viafiller 160, and the capping layer 140 are sequentially etched using thephotoresist pattern 185 as an etch mask, and then the ILD 130 and thevia filler 160 are etched to a predetermined depth, thereby forming thetrench 190. The trench 190 is dry etched on condition that an etch ratioof the ILD 130 to the via filler 160 is 1:1, or 4:1 or less. Therefore,fence defects (see FIG. 1) can be prevented and, since a portion of thevia filler 160 still remains in the via 150, it can prevent the etchstop layer 120 from being etched to damage the lower interconnection110. If the ILD 130 is formed of an OSG and the via filler 160 is formedof an HSQ-based material, both of them have characteristics of inorganicmaterials. Thus, if an RIE process is carried out using a mixture of amain etch gas (e.g., CxFy and CxHyFz), an inert gas (e.g. Ar gas), andoptionally at least one of O₂, N₂, and COx, the foregoing condition foretching the trench 190 can be satisfied.

[0045]FIG. 11 is a cross-sectional view of the resultant structure, fromwhich the photoresist pattern 185 a and the remaining via filler 160 areremoved. After the etching of the trench 190 is completed, thephotoresist pattern 185 a is removed using H₂-based plasma obtained fromH₂, N₂/H₂, NH₃/H₂, NH₃/H₂, He/H₂, or a mixture thereof. Next, the viafiller 160 is removed, thereby forming a dual damascene interconnectionregion 195, which includes the via 150 and the trench 190. The viafiller 160 is removed using a wet etch process. The wet etch process forremoving the via filler 160 is carried out on condition that the ILD 130is only slightly etched and only the via filler 160 is selectivelyremoved, i.e., that a wet etch ratio of the via filler 160 to the ILD130 is 20:1 or higher. Also, the via filler 160 should have an etchselectivity with respect to the etch stop layer 120. While the ILD 130has organic characteristics, the via filler 160 and the etch stop layer120 are formed of inorganic materials. Thus, to satisfy the condition,the via filler 120 is removed by wet etching using an etchant having ahigh selectivity with respect to organic materials. In particular, ifthe via filler 160 is formed of an HSQ-based material, the ILD 130 isformed of an OSG, and the etch stop layer 160 is formed of SiC(N), thevia filler 160 may be wet etched in an HF solution diluted withdeionized water (DIW), or a buffered oxide etchant (BOE), which is amixture of NH₄, HF, and deionized water. Preferably, the diluted HFsolution is in a ratio of 100(DIW):1(HF) or higher. Thus, an etch ratioof HSQ-based material to OSG to SiC(N) can be higher than 100:1:1. Inaddition, etching of the ILD 130 can be prevented during the removal ofthe via filler 160 so as to precisely control the critical dimension ofthe trench 190.

[0046] A detailed description of the via etching, the trench etching,and the wet etching is given in Korean Patent Application No.2002-57192, commonly owned by the same assignee and incorporated hereinby reference in its entirety as fully disclosed in the presentinvention.

[0047] Referring to FIG. 12, the etch stop layer 120 exposed in the via150 is etched until the lower interconnection 110 is exposed, therebycompleting the dual damascene interconnection region 195. The etch stoplayer 120 is etched so that the lower interconnection 110 is notaffected and only the etch stop layer 120 is selectively removed.

[0048] Referring to FIG. 13, a conductive layer is formed on the dualdamascene interconnection region 195 and then planarized, therebyforming a dual damascene interconnection 210. The conductive layer isformed of aluminum, tungsten, copper, or any alloy thereof, and mostpreferably formed of copper because of its low resistance. Also, theconductive layer may be a stack of a diffusion barrier layer and a maininterconnection layer, or may be embodied in various other forms byknown methods.

[0049] It is obvious that the via-first dual damascene process describedwith reference to FIGS. 2 through 13 can be applied to a trench-firstdual damascene process.

[0050] The present invention will be described in more detail withreference to the following experimental examples. Here, it is obviousthat the present invention is not limited to the experimental examples.

[0051] The following experimental examples were obtained in a process offabricating dual damascene interconnections of a 90 nm-design-rule logicdevice with embedded 1.1 μm² 6Tr-SRAM.

EXPERIMENTAL EXAMPLE 1

[0052] An etch stop layer was formed using SiC(k=5.0), an ILD was formedof CVD OSG(k=2.9) to a thickness of 7000 Å, and a via having a diameterof 0.132 μm was formed. Next, HSQ(Fox™ of Dow Corning Corp.) for a viafiller was formed using spin coating. FIGS. 14A and 14B are SEM imagesshowing cross-sectional views of a test sample, in which the HSQ viafiller is filled. Referring to FIGS. 14A and 14B, it can be seen thatthe HSQ had a good gap filling characteristic and was formed in a planarfashion on an OSG layer. Also, a difference between the thickness T1(FIG. 14A) of the HSQ layer formed in the low via-density region and thethickness T2 (FIG. 14B) of the HSQ layer formed in the high via-densityregion was 2000 Å or less.

EXPERIMENTAL EXAMPLE 2

[0053] An HSQ layer was formed in the same manner as in Experimentalexample 1, and then an organic ARL and a photoresist for KrF weresequentially formed on the HSQ layer. An exposure process was conductedusing an exposure source with a wavelength of 248 nm and a developmentprocess was carried out using a tetramethyl ammonium hydroxidedeveloping solution, thereby forming a photoresist pattern defining atrench. As a result, a test sample was prepared.

[0054] A contrastive sample was prepared by forming a photoresistpattern defining a trench directly on an HSQ layer.

[0055]FIG. 15A is an SEM image of the test sample, while 15B is an SEMimage of the contrastive sample. FIGS. 15A and 15B confirm that areliable photoresist pattern was obtained by forming an organic ARL.

EXPERIMENTAL EXAMPLE 3

[0056] An HSQ layer was formed in the same manner as in Experimentalexample 1, the surface of the HSQ layer was processed using plasma, andan organic ARL was formed. Next, a photoresist for KrF was coated on theorganic ARL. An exposure process was conducted using an exposure sourcewith a wavelength of 248 nm and a development process was carried outusing a tetramethyl ammonium hydroxide developing solution, therebyforming a photoresist pattern defining a trench. As a result, a testsample was prepared.

[0057] A contrastive sample was prepared by using an organic ARL for avia filler in place of an HSQ layer and forming a photoresist pattern.

[0058]FIG. 16A is an SEM image of the test sample, while 16B is an SEMimage of the contrastive sample. Referring to FIG. 16A, the HSQ viafiller functioned as a diffusion barrier layer to basic materials, suchas amine, so that a reliable photoresist pattern could be formed. Incontrast, referring to FIG. 16B, when the organic ARL was used as thevia filler, basic materials diffused and neutralized acids H+ in aphotoresist layer, thereby forming a damaged photoresist pattern.

EXPERIMENTAL EXAMPLE 4

[0059] A photoresist pattern was formed in the same manner as inExperimental example 3, and a trench was formed by performing a dry etchprocess using a CxFy main etch gas such that an etch ratio of HSQ:OSGwas 1:1. Thus, a test sample was prepared. FIGS. 17A and 17B are SEMimages of the test sample. FIG. 17A is a cross-sectional view takenalong the width of the trench, while FIG. 17B is a cross-sectional viewtaken along the length of the trench. Referring to FIGS. 17A and 17B, itcan be seen that a good trench profile was formed in a dual damasceneregion, and although over-etching of about 50% occurred, the HSQ viafiller reliably protected a SiC etch stop layer.

EXPERIMENTAL EXAMPLE 5

[0060] A trench was formed in the same manner as in Experimental example4, an HSQ layer remaining in a via was removed using a diluted HFsolution in a ratio of 500(DIW):1(HF). Thus, a test sample was prepared.FIG. 18 is an SEM image of the test sample. Referring to FIG. 18, theHSQ layer was completely removed, and a robust and reliable dualdamascene region having a good profile and a desired critical dimensionwas formed without generation of fences.

EXPERIMENTAL EXAMPLE 6

[0061] A dual damascene region was formed according to a process offabricating a test sample as in Experimental examples 1-5, and a copperinterconnection was formed in the dual damascene region, using a typicalcopper interconnection fabrication process. The dual damasceneinterconnection fabrication process was repeated two or more times,thereby completing 9-level dual damascene interconnections of a 90nm-design-rule logic device with embedded 1.1 μm² 6Tr-SRAM. FIG. 19 isan SEM image of the logic device. FIG. 19 confirms that non-defectiveand reliable devices with a fine design rule can be fabricated accordingto the method of the present invention.

EXPERIMENTAL EXAMPLE 7

[0062] Electrical characteristics of the device fabricated inExperimental example 6 were measured. FIGS. 20 through 24 show theresults.

[0063] Referring to FIGS. 20 and 21, it can be seen that the resultingdual damascene structure had good via resistance characteristics.

[0064] Referring to FIG. 22, it can be seen that even if the resultingdevice was annealed at a temperature of 400° C. for 6 hours, the viaresistance characteristics were not degraded.

[0065] In another method, a device was formed in the same manner as inExperimental example 6, except that the line and the space ofinterconnections were changed to 0.14 μm and 0.12 μm, respectively. FIG.23 shows results of measuring sheet resistance and leakage current ofthe interconnections.

[0066] Referring to FIG. 23, the sheet resistance and the leakagecurrent were in good condition.

[0067]FIG. 24 shows an RC value of the device fabricated according toExperimental example 6 and an RC value of a device in which an etch stoplayer is formed of SiN and an ILD is formed of SiOF.

[0068] Referring to FIG. 24, when the etch stop layer was formed of SiCand the ILD was formed of OSG as in the present invention, an RC valuewas reduced to about 20% compared with the conventional device in whichthe etch stop layer is formed of SiN and the ILD is formed of SiOF.

[0069] According to the present invention, an ILD is formed of a low-kdielectric material such that an RC delay is prevented and cross talkand power consumption can be minimized. Also, the ILD is formed of ahybrid low-k dielectric material and a via filler is formed of acarbon-free inorganic material. As a result, an etch stop layer coveringa lower interconnection is protected, photoresist poisoning isprevented, a DOF margin is improved in a photolithographic process,fences, which may adversely affect electrical properties of dualdamascene interconnections, are prevented, and the width and thecritical dimension of a trench can be held constant.

[0070] While the present invention has been particularly shown anddescribed with reference to preferred embodiments thereof, it will beunderstood by those of ordinary skill in the art that various changes inform and details may be made therein without departing from the spiritand scope of the present invention as defined by the following claims.

What is claimed is:
 1. A method of fabricating dual damasceneinterconnections, the method comprising: (a) forming on a substrate ahybrid dielectric layer having a dielectric constant of 3.3 or less; (b)forming a via in the dielectric layer; (c) filling the via with acarbon-free inorganic filler; (d) partially etching the inorganic fillerfilling the via and the dielectric layer to form a trench, which isconnected to the via and in which interconnections will be formed; (e)removing the inorganic filler remaining in the via; and (f) completinginterconnections by filling the trench and the via with interconnectionmaterial.
 2. The method of claim 1, further comprising, before step(a),: forming a lower interconnection on the substrate; and forming anetch stop layer on the lower interconnection.
 3. The method of claim 2,wherein the etch stop layer is formed of at least one of SiC, SiN, andSiCN.
 4. The method of claim 1, wherein the hybrid dielectric layerhaving a dielectric constant of 3.3 or less is an organo silicate glasslayer.
 5. The method of claim 1, wherein the hybrid dielectric layerhaving a dielectric constant of 3.3 or less is formed using chemicalvapor deposition.
 6. The method of claim 1, further comprising, beforestep (b), forming a capping layer on the hybrid dielectric layer havinga dielectric constant of 3.3 or less, wherein in step (b), a via isformed in the capping layer and the dielectric layer.
 7. The method ofclaim 6, wherein the capping layer is formed of an anti-reflectivematerial.
 8. The method of claim 6, wherein the capping layer is formedof at least one of SiO₂, SiOF, SiON, SiC, SiN and SiCN.
 9. The method ofclaim 2, wherein step (b) comprises: forming a photoresist pattern onthe dielectric layer to define the via; and forming the via exposing theetch stop layer by dry etching the dielectric layer using thephotoresist pattern as an etch mask.
 10. The method of claim 1, whereinthe carbon-free inorganic filler is an HSQ-based filler.
 11. The methodof claim 1, wherein the carbon-free inorganic filler further includes alight absorption material and/or a dissolution inhibitor for aphotoresist developing solution.
 12. The method of claim 1, furthercomprising, before step (d), at least one of (i) processing the surfaceof the carbon-free inorganic filler using plasma, (ii) forming ananti-reflection layer on the surface of the carbon-free inorganicfiller, and (iii) processing the surface of the carbon-free inorganicfiller using plasma and forming an anti-reflection layer on theplasma-processed surface of the carbon-free inorganic filler.
 13. Themethod of claim 12, wherein the plasma is derived from O₂, H₂, He, NH₃,N₂, Ar, or any mixture thereof.
 14. The method of claim 12, wherein theanti-reflection layer is an organic anti-reflection layer.
 15. Themethod of claim 14, wherein the anti-reflection layer is formed to athickness of about 500 Å to 700 Å.
 16. The method of claim 1, whereinstep (d) includes: forming a photoresist pattern on the inorganic fillerto define the trench; forming the trench by dry etching using thephotoresist pattern as an etch mask such that an etch ratio of theinorganic filler to the dielectric layer is 4:1 or lower; and removingthe photoresist pattern.
 17. The method of claim 16, wherein the dryetching uses CxFy or CxHyFz as a main etching gas, and removing thephotoresist pattern uses an H₂-based plasma.
 18. The method of claim 1,wherein step (e) comprises wet etching such that an etch ratio of theinorganic filler to the dielectric layer is 20:1 or higher.
 19. Themethod of claim 18, wherein the wet etching uses diluted HF, a mixtureof NH₄F, HF, and deionized water.
 20. The method of claim 1, wherein instep (F), the interconnection is a copper interconnection.
 21. A methodof fabricating dual damascene interconnections, the method comprising:(a) forming an organo silicate glass layer on a substrate; (b) forming avia in the organo silicate glass layer; (c) filling the via with anHSQ-based filler; (d) partially etching the HSQ-based filler filling thevia and the organo silicate glass layer to form a trench, which isconnected to the via and in which interconnections will be formed; (e)removing the HSQ-based filler remaining in the via; and (f) completinginterconnections by filling the trench and the via with aninterconnection material.
 22. The method of claim 21, wherein in step(a), the organo silicate glass layer is formed using chemical vapordeposition.
 23. The method of claim 21, further comprising, before step(a),: forming a lower interconnection on the substrate; and forming anetch stop layer on the lower interconnection.
 24. The method of claim23, wherein the etch stop layer is formed of at least one of SiC, SiN,and SiCN.
 25. The method of claim 21, further comprising, before step(b), forming a capping layer on the organo silicate glass layer.
 26. Themethod of claim 25, wherein the capping layer is formed of ananti-reflective material.
 27. The method of claim 25, wherein thecapping layer is formed of at least one of SiO₂, SiOF, SiON, SiC, SiN,and SiCN.
 28. The method of claim 23, wherein step (b) comprises:forming a photoresist pattern on the organo silicate glass layer todefine the via; and forming the via exposing the etch stop layer by dryetching the organo silicate glass layer using the photoresist pattern asan etch mask.
 29. The method of claim 21, wherein the HSQ-based fillerfurther includes a light absorption material and/or a dissolutioninhibitor for a photoresist developing solution.
 30. The method of claim21, further comprising, before step (d), at least one of (i) processingthe surface of the HSQ-based filler using plasma, (ii) forming ananti-reflection layer on the surface of the HSQ-based filler, and (iii)processing the surface of the HSQ-based filler using plasma and thenforming an anti-reflection layer on the plasma-processed surface of theHSQ-based filler.
 31. The method of claim 30, wherein the plasma is O₂,H₂, He, NH₃, N₂, Ar, or any mixture thereof.
 32. The method of claim 30,wherein the anti-reflection layer is an organic anti-reflection layer.33. The method of claim 32, wherein the anti-reflection layer is formedto a thickness of about 500 Å to 700 Å.
 34. The method of claim 21,wherein step (d) includes: forming a photoresist pattern on theHSQ-based filler to define the trench; forming the trench by dry etchingusing the photoresist pattern as an etch mask such that an etch ratio ofthe HSQ-based filler to the organo silicate glass layer is 4:1 or lower;and removing the photoresist pattern.
 35. The method of claim 34,wherein the dry etching uses CxFy or CxHyFz as a main etching gas, andremoving the photoresist pattern uses an H₂-based plasma.
 36. The methodof claim 21, wherein step (e) comprises wet etching such that an etchratio of the HSQ-based filler to the organo silicate glass layer is 20:1or higher.
 37. The method of claim 36, wherein the wet etching usesdiluted HF or a mixture of NH₄F, HF, and deionized water.
 38. The methodof claim 21, wherein in step (f), the interconnection is a copperinterconnection.
 39. A method of fabricating dual damasceneinterconnections, the method comprising: (a) forming a lowerinterconnection on a substrate; (b) forming an etch stop layer on thelower interconnection; (c) forming an organo silicate glass layer usingchemical vapor deposition on the etch stop layer; (d) forming a viathrough the organo silicate glass layer to expose the etch stop layer;(e) filling the via with an HSQ-based filler; (f) processing the surfaceof the HSQ-based filler using plasma; (g) forming an anti-reflectionlayer on the plasma-processed surface of the HSQ-based filler; (h)partially etching the anti-reflection layer, the HSQ-based fillerfilling the via, and the organo silicate glass layer to form a trench,which is connected to the via and in which interconnections will beformed; (i) removing the HSQ-based filler remaining in the via; and (k)completing interconnections by filling the trench and the vias with aninterconnection material.
 40. The method of claim 39, wherein the etchstop layer is formed of at least one of SiC, SiN, and SiCN.
 41. Themethod of claim 39, before step (d), further comprising forming acapping layer on the organo silicate glass layer.
 42. The method ofclaim 41, wherein the capping layer is formed of an anti-reflectivematerial.
 43. The method of claim 41, wherein the capping layer isformed of at least one of SiO₂, SiOF, SiON, SiC, SiN, and SiCN.
 44. Themethod of claim 39, wherein the HSQ-based filler further includes alight absorption material and/or a dissolution inhibitor for aphotoresist developing solution.
 45. The method of claim 39, wherein theplasma is O₂, H₂, He, NH₃, N₂, Ar, or any mixture thereof.
 46. Themethod of claim 39, wherein the anti-reflection layer is an organicanti-reflection layer.
 47. The method of claim 46, wherein theanti-reflection layer is formed to a thickness of about 500 Å to 700 Å.48. The method of claim 39, wherein step (h) includes: forming aphotoresist pattern on the anti-reflection layer to define the trench;forming the trench by dry etching using the photoresist pattern as anetch mask such that an etch ratio of the HSQ-based filler to the organosilicate glass layer is 4:1 or lower; and removing the photoresistpattern.
 49. The method of claim 48, wherein the dry etching uses CxFyor CxHyFz as a main etching gas, and removing the photoresist patternuses an H₂-based plasma.
 50. The method of claim 39, wherein step (i)comprises wet etching such that an etch ratio of the HSQ-based filler tothe organo silicate glass layer is 20:1 or higher.
 51. The method ofclaim 50, wherein the wet etching uses diluted HF or a mixture of NH₄F,HF, and deionized water.
 52. The method of claim 39, wherein in step(k), the interconnection is a copper interconnection.